While the VIC-II chip has a very good documentation on zimmers none has created a similar document for the TED. I would like to understand the internals of TED so I started to analyze the signals inside a plus4 with a logic sniffer. One critical part is the timing on the system bus between TED the CPU and the memory (bus protocol). One thing I don't understand is how the MUX signal is created by TED from the clock signals (using the 17.7Mhz PAL or 14.3 NTSC clock?). Does anyone know whether there is any rule how to produce the MUX signal? Any logic equiation? As I can see it this is similar to a clock signal but it doesn't have symmetric duty cycle. It is somehow tied to the CPU clock and most probably delayed with half a CPU clock cycle. Bil do you have any idea how to produce it? Does it use phi1 and phi2 clocks which are not produced by the 7501 CPU but maybe the TED internally? Also, how is RAS and CAS related to the MUX signal?
Any hint would be good!