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HMOS-II VIC II or is it a IIe?

I've been looking at reverse engineering/having a poke around the VIC II chip as shoot here http://visual6502.org/images/pages/Commodore_8565_die_shots.html This is the HMOS-II PAL B version.
Problem No 1.
The VIC II is a 40 pin chip, there are 46pads.
Problem No 2.
The pads and their mode don't line up. Here are the pin descriptions and I have marked what mode each pin needs to be

Pin 6566 6567/6569 8565 Dir  

1 DB6  DB6                            Bi
 2 DB5  DB5                            Bi
 3 DB4  DB4                            Bi
 4 DB3  DB3                            Bi
 5 DB2  DB2                            Bi
 6 DB1  DB1                            Bi
 7 DB0  DB0                            Bi
 8 /IRQ  /IRQ                           Out
 9 LP  LP   light pen                 In
10 /CS  /CS                            In
11 R/W  R/W                            Bi
12 BA  BA                             Out
13 Vdd (+12V) Vdd (+12V) Vdd (+5V)      In
14 Color  Color                          Out
15 S/LUM  S/LUM                          Out
16 AEC  AEC                            Out
17 PH0  PH0                            Out
18 PHIN  /RAS                           Out
19 PHCOL  /CAS                           Out
20 Vss  Vss                            In  ( gnd )

 

21 A0  PHCL                           In Colour clock 17mhz
22 A1  PHIN                           In Dot Clock 7.88
23 A2  A11                            Out ?
24 A3  A0 (A8)                        BI
25 A4  A1 (A9)                        Bi
26 A5  A2 (A10)                       Bi
27 A6  A3 (A11)                       Bi
28 A7  A4 (A12)                       Bi
29 A8  A5 (A13)                       Bi
30 A9  A6 ("1")                       Bi
31 A10  A7                             Out ?
32 A11  A8                             Out ?
33 A12  A9                             Out ?
34 A13  A10                            Out ?
35 DB11  DB11                           In
36 DB10  DB10                           In
37 DB9  DB9                            In
38 DB8  DB8                            In
39 DB7  DB7                            Bi
40 Vcc  Vcc  Vcc            In  ( 5V)

 
 
(Edit - the HTML table doesn't work on the post, also tried formatted and using code tags and font tags still no dice - how to I make this readable? )

The 6566 is not used by Commodore, and the 8565 matchs the 6569 pins unless changed.

 

From looking at the Chip you can see a nice big 10 bit wide 40 bit high shift register. 10 bits being 8 bits for screen code and 4 bits for Colour data. Given DB10-7 are wired to the CRAM chip those lines have to be the Colour data and only the colour data. Right next to the bottom Power Rail are 4 In only pads directly connected to the shift register. This makes me failry confident that the bottom power rail is Vcc and that to the left of it is DB 7-10.  The pin description then goes into the Address Bus Out onl,y to which there is a bunch of those then to some Bi pads. Looks good right.

 

This makes the bottom power pad pin 40 so the top power pad is thus 20. But there is an extra pad between the them. I like the pad with the two massive caps on it for A6 as this multiplexes to "1" but it doesn't seem to have an input driver. None the less if we take 20 to be the top pin, and count counterclock down we get two input pins ( which lines up as they are the clock ins ) then A11 as output, A0,1,2,3,4,5 as Bi, A6 with its Caps, A7,8,9,10 as out. And then 1 extra out pad before DB11...?

 

 

Going clockwse from VSS gets into a mess fast, /CAS massive out driver good, /RAS again good, Phi 0 massive out driver...um no?

The 3rd pad down on the right side has to be VDD due to the large amount of metal.

D7 being left of Vcc then D6,5,4,3,2,1,0 being on the right makes sense. But then the next pad looks to be input and its meant to be /IRQ

 

This also leaves the case of what about the 6 other pads...

This is where the VIC IIe comes in, it is 8566 ( so the next chip then ) and is a 48pin DIL with 2 NCs = 46, so are all 8565s also 8566s? Did Commodore make one die for both the 64 and 128 and is Vdd is used to switch modes? As the VIC IIe doesn't have Vdd 

 

Anything you can shed on this mystery Bil?
 

Edited by: Oziphantom on 2015-11-21 03:14
8566 is not the same

Look no further than http://segher.ircgeeks.net/vic-ii/ :-)

The 8565-blocks.{jpg,xcf} shows all the pads, and names the functional
blocks. The 8565R2.xcf is my Gimp file where I labeled pretty much
every single signal on the chip.

There are five (octagonal, smaller) pads to the right. Those are four
color output bits (0 is black, 1 is white, 2 is red, 15 is light gray,
etc.), and a frame signal. I believe those are test pads.

The pad on the middle left is to connect the back bias generator to the
substrate.

The 8566 is a different die. It has some registers that are physically
not there on the 8565.

Cool, I used to have one of
Cool, I used to have one of these plots hanging in my office.
Nice work :) Saves me a lot
Nice work :) Saves me a lot of work ;) I am right in thinking that # means Not? so A0 is A0 and #A0 is the inverted A0. If only those pads where on pins, it would save the digital out dilemma right there... Oh well no tricking a 64 into 2Mhz mode ;)
You're welcome.

You're welcome.

Yes, # means not. It is the same as an overbar over the symbol. Some people write # after the symbol
instead, or write n or n_ before it. I like # because it is very visual, and I can actually type it :-) # on a pad
is best thought of as low active. like #IRQ is pulled low to trigger an interrupt, or R/#W means high for
read, low for write.

If you decap a chip, those pads might be exposed through overglass holes. I don't know.

I have never seen 8566 (VIC IIe) or 6566 (original VIC II, used in the MAX machine) die photographs.
The 8566 should have some extra circuitry, it's not obvious how that will fit in; probably it is all just
tucked away to a side ;-)

The 8565 (this chip) is a lot like the older 6569. The analogue portions (top right corner) have
different sizing; the RAS/CAS things are different, those depend on delays other than those
given by the clocks; back bias gen is different. That is about it.

In the oldest revisions of the 6569 there was a bug with the light pen (LP) interface, it had the
timing wrong. Supposedly old 6567 (NTSC version) dies had only five levels of luminosity,
not nine. Differences between the different region dies are (almost?) exclusively the X and Y
match ROMs.

The 6566 was first, and it didn't drive dynamic RAM, just static RAM. It had fourteen address
pins, not multiplexed, and no RAS and CAS. It should look nicer since the DRAM features
are rather tucked on. As said, the RAS/CAS do not really fit in with designed timing signals
on the chip (they time themselves, big delay chains etc.); and there is all this weird address
muxing (top left of the chip).

You see, the DRAM of the time had the address fed to them in two phases. First you had
RAS, "row address select", which selects one out of 128 or 256 rows; and then CAS, column
address select, which picks one of the 128 or 256 columns out of that row, and inputs/outputs
that bit (yes, bit, you have 8 chips in parallel to make a byte-wise system).

The VIC can handle either 128 or 256, with a small change to its metal layer. If you look at
the A11 pad, there are two biggish strips of polysilicon to the right of them, under the ground
ring. You see one connects to ground, and the other to 5V; the contacts are there for them
to be flipped around. The signals from there (I think I called them sa7, sa8; "select 8-bit
address") go to muxes, selecting the "high" address half; and then to muxes selecting high
or low. That is all in the top-left corner, above the clock drivers.

DRAM also needs periodic refresh: each row needs to be accessed periodically. That is
done by doing five accesses ever scan line, with a counter that just counts up. If you look
really carefully you'll see that it only counts seven bits, not eight; most chips only need to
have seven bits refresh though (old DRAM chips only *had* seven bits for the rows, many
refresh circuits only did seven, DRAM manufacturers wanted their new bigger chips to
work on those as well, those chips refresh two rows at once).

I can probably go on, If you have any questions... But first look at the chip :-)

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